Fraunhofer Heinrich Hertz Institute 		 
     

Jens Brandenburg
     

Video Coding & Analytics Department
      Image & Video Coding Group
      Contact  
         
      Fraunhofer Institute for Telecommunications
Heinrich Hertz Institute
Einsteinufer 37
10587 Berlin
Germany


Tel:  +49 30 31002-660
Fax: +49 30 31002-190


jens.brandenburg@hhi.fraunhofer.de
         
      Publications  
     

    2017

  • Jens Brandenburg and Benno Stabernack:
    Simulation-based HW/SW co-exploration of the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi-core architectures,
    Journal of Systems Architecture, vol. 77, pp. 26-42, 2017,
    doi:10.1016/j.sysarc.2016.12.009.


    • 2016

  • Jens Brandenburg and Benno Stabernack:
    Simulation based Analysis of Memory Access Conflicts for Heterogeneous Multi-Core Platforms,
    Proceddings of the 29th International Conference on Architecture of Computing Systems (ARCS'16), Nürnberg, Germany, April 4, 2016.


    • 2015

  • Jens Brandenburg and Benno Stabernack:
    Exploring the Concurrent Execution of HEVC Intra Encoding Algorithms for Heterogeneous Multi Core Architectures,
    Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP'15), Cracow, Poland, September 23-25, 2015,
    doi:10.1109/DASIP.2015.7367268.

  • Benno Stabernack, Jan Möller, Jan Hahlbeck and Jens Brandenburg:
    Demonstrating an FPGA Implementation of a Full HD Real-time HEVC Decoder with Memory Optimizations for Range Extensions Support,
    Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP'15), Cracow, Poland, September 23-25, 2015, Demo Night Paper at DASIP2015,
    doi:10.1109/DASIP.2015.7367247.


    • 2013

  • Jens Brandenburg and Benno Stabernack:
    Memory Access Analysis and Optimization of a Parallel H.264/SVC Decoder for an Embedded Multi-Core Platform,
    Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing (DASIP'13), pp. 304-311, Cagliari, Italy, October 8-10, 2013.

  • Benjamin Bross, Valeri George, Mauricio Alvarez-Mesa, Tobias Mayer, Chi Ching Chi, Jens Brandenburg, Thomas Schierl, Detlev Marpe, and Ben Juurlink:
    HEVC Performance and Complexity for 4K Video,
    IEEE International Conference on Consumer Electronics (ICCE'13), pp. 44-47, Berlin, Germany, September 2013, Best Paper Award of the 2013 IEEE International Conference on Consumer Electronics - Berlin,
    doi:10.1109/ICCE-Berlin.2013.6698051.

  • A. Bartzas, P.Bellasi, J.Brandenburg, W.Fornaciari, I.Koutras, G.Massari, G.Palermo, E.Paone, C.Silvano, D.Soudris, S.Xydis, V.Zaccaria:
    Cooperative Design Space Exploration and Run-Time Resource Management for Application Adaptivity on Multi-Core Platforms: A Networked Video Surveillance Use Case,
    DATE Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools and Applications, Grenoble, France, March 22, 2013, Poster at DEPCP2013.

  • Jens Brandenburg and Benno Stabernack:
    Performance and Memory Access Analysis for Embedded Multi-Core Media Signal Processing Platforms using NoCTrace,
    HiPEAC Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms, Berlin, Germany, January 22, 2013, Poster at DITAM 2013.


    • 2012

  • Benno Stabernack and Jens Brandenburg:
    A Novel Profiling Methodology for Many-Core Simulation Models aiming HW/SW Co-Optimization,
    DATE Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools and Applications, Dresden, Germany, March 16, 2012, Poster at DEPCP2012.

  • Jens Brandenburg and Benno Stabernack:
    A Generic and Non-Intrusive Profiling Methodology for SystemC Multi-Core Platform Simulation Models,
    Proceedings of the 25th Architecture of Computing Systems Conference (ARCS'12), pp. 135-146, Munich, Germany, February 28 - March 02, 2012,
    doi:10.1007/978-3-642-28293-5_12.

  • Benno Stabernack and Jens Brandenburg:
    NoCTrace - A Non Intrusive System Level Architecture Exploration Tool for Network on Chip Architectures,
    HiPEAC Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms, Paris, France, January 24, 2012, Poster at DITAM2012.


    • 2011

  • C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara, D. Melpignano, J.-M. Zins, D. Siorpaes, H. Hubert, Benno Stabernack, Jens Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, R. Leupers, H. Meyr, J. Ansari, P. Mahonen and B. Vanthournout:
    2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures,
    VLSI 2010 Annual Symposium, Selected Papers, Editors: N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, M. Huebner, Lecture Notes in Electrical Engineering, Springer Netherlands, vol. 57, pp. 65-79, August 31, 2011, ISBN 978-94-007-1487-8,
    doi:10.1007/978-94-007-1488-5_5.

  • C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, E. Speziale, D. Melpignano, J.M. Zins, H. Hubert, Benno Stabernack, Jens Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, D. Soudris, T. Kempf, G. Ascheid, H. Meyr, and J. Ansari, P. Mahonen, and B. Vanthournout:
    Parallel Paradigms and Run-time Management Techniques for Many-core Architectures: The 2PARMA Approach,
    Proceedings of IEEE 9th International Conference on Industrial Informatics (INDIN'11), Caparica, Lisbon, Portugal, July 26-29, 2011,
    doi:10.1109/INDIN.2011.6035001.

  • C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, E. Speziale, D. Melpignano, J.M. Zins, H. Hubert, Benno Stabernack, Jens Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, I. Anagnostopoulos, A. Bartzas, D. Soudris, T. Kempf, G. Ascheid, H. Meyr, J. Ansari, P. Mahonen, and B. Vanthournout:
    Parallel programming and Run-time Resource Management Framework for Many-core Platforms: The 2PARMA Approach,
    Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'11), Montpellier, France, June 20-22, 2011, Invited Paper,
    doi:10.1109/ReCoSoC.2011.5981522.

  • Benno Stabernack and Jens Brandenburg:
    NoCTrace - A System Level Architecture Exploration Tool for Network on Chip Architectures,
    DATE Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools and Applications, Grenoble, France, March 18, 2011, Poster at DEPCP2011.


    • 2010

  • C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara, D. Siorpaes, H. Hübert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, H. Meyr, J. Ansari, P. Mähönen, and B. Vanthournout:
    2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures,
    IEEE Computer Society, Annual Symposium on VLSI 2010, Lixouri, Kefalonia, Greece, July 2010,
    doi:10.1109/ISVLSI.2010.93.

  • Thomas Wirth, Lars Thiele, Thomas Haustein, Jens Brandenburg and Benno Stabernack:
    Scalable Video Broadcasting Trials in 4G Cellular Deployments,
    Proceedings of the 2010 Future Network Mobile Summit (FNMS'10), Florence, Italy, June 2010.


    • 2009

  • Benno Stabernack, Heiko Hübert, Jens Brandenburg, and Jan Möller:
    An Experimental Mobile Terminal for Scalable Video Coding Applications using a H.264/AVC Decoder SOC,
    Proceedings of 13th IEEE International Symposium on Consumer Electronics (ISCE'09), pp. 54-57, Mielparque-Kyoto, Kyoto, Japan, May 25-28, 2009,
    doi:10.1109/ISCE.2009.5156964.

     

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